Cost-effective fixed-point hardware support for RISC-V embedded systems

Hardware/Software Codesign for Embedded RISC Core

This paper describes hardware/software codesign method of the extendible embedded RISC core VIRGO, which based on MIPS-I instruction set architecture. VIRGO is described by Verilog hardware description language that has five-stage pipeline with shared 32-bit cache/memory interface, and it is controlled by distributed control scheme. Every pipeline stage has one small controller, which controls ...

Hardware Support for Embedded Java

The general Java runtime environment is resource hungry and unfriendly for realtime systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables worst-case execution time analysis of Java programs. This chapter gives an overview of current appr...

Support for Hardware Devices in Component Models for Embedded Systems

Hardware accelerated approach for floating-point multiplication on 32-bit pipelined RISC-V processor

Implementing hardware support for all extensions of the RISC-V Instruction Set Architecture inside a processor would lead to avoidable area and power consumption for applications that rarely utilize a particular extension. In this paper, authors have first suggested a modified 3-stage pipeline alternative to the ZSCALE processor (32-bit) by UC Berkeley. Subsequently a hardware-accelerated appro...

A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core

MPEG-2 audio decoding algorithms are involved of several complex coding techniques and therefore difficult to be implemented by an efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG-2 audio decoder. The MPEG-2 audio algorithms can be roughly divided into two types of operations. The first type is regular but computation-intensive such as fi...